1. Field of the Invention
This invention relates to a microprogramming control system, and more particularly to a microprogramming control system, in with which it is possible to read out micro instructions at the same speed as that for readout of micro instructions in the prior art, although using a control memory of lower read rate performance than a conventional one.
2. Description of the Prior Art
Readout, interpretation and execution of micro instructions can be realized by several tens of combinations of basic operations such as transfer between registers, starting of a main memory, an offset, the use of adder, etc. Recently, micro program processing, has been employed, in which instructions (micro instructions) designating the basic operations are gathered, stored in a control memory and sequentially read out in the unit of each micro instruction for execution. The group of gathered micro instructions is called a micro program; and the control system for this micro program is called a micro program control system.
With reference to FIGS. 1, 2 and 3, a conventional micro program control system will be described.
In FIG. 1, a leading address of a microprogram, corresponding to a micro instruction, is set in an address register AR. The leading address is decoded by a decoder DEC and applied to a control memory CM. A micro instruction corresponding to the leading address is then read out from control memory CM. The read-out micro instruction is stored in a data register DR. One part of the micro instruction stored in the data register DR is applied to the address register AR for designating the address of the next micro instruction and the remaining part of the micro instruction is used as a control system FN for controlling the operation of a computer.
In this case, since the processing speed of the computer is dependent upon the read rate of the micro instruction, it is desired to increase the micro instruction read rate as high as possible. Therefore, a memory capable of high-speed processing is generally employed, since the speed of a memory used as the control memory CM usually occupies the larger part of the micro instruction read time. However, such a memory capable of high-speed processing is expensive, and hence is a bottleneck in the production of inexpensive computers.
Further, with the system of FIG. 1, in the case of a conditional branch corresponding to a certain condition, a new address is determined according to the condition and the next micro instruction is read out in accordance with the new address. Accordingly, the micro instruction which is read out in accordance with the preceding micro instruction, at the instant when the new address is determined according to the condition, is invalidated and the next micro instruction according to the new address is used for branch. This imposes a substantial limitation on the high-speed processing. However, processing according to microprogramming is usually adapted to be achieved in a predetermined mode of execution. Therefore, even if branch exists in the processing, the next step is determined according to the branch so that an instruction following the branch can be read out regardless of the condition.
To avoid the above state, a system shown in FIG. 2 has been adopted in the prior art. FIG. 2 shows in block form this system and FIG. 3 is a time chart of its operation. The control system of FIG. 2 is adapted such that an address indicated by the address register AR is decoded by the decoder DEC and applied to the control memory CM, whereby two micro instructions can be read out. In accordance with the result of a branch operation instructed by the control signal portion of the preceding micro instruction, a gating signal is developed which causes selection of one of the two micro instructions thus read out and its application to the data register DR, thereby blocking the application of the other micro instruction. The system, of selecting one of the two micro instructions, by the control system of FIG. 2, makes it possible to eliminate the waste time of the FIG. 1 system since the branch operation is caused by the control signal portion of the preceding micro instruction and a micro instruction is present at the input to the branch.
FIG. 3 is a time chart, for explaining the operations of respective parts of the system depicted in FIG. 2. Reference characters t.sub.0, t.sub.1, t.sub.2, . . . indicate time cycles by a basic clock of the computer. Upon setting of the next address in the address register AR in the time cycle t.sub.1, designated micro instructions are read out from the parts EVEN and ODD of the control memory CM, respectively, and, according to the result of an operation by the preceding micro instruction, a flip-flop F/F is actuated and read-out data of either one of the parts EVEN or ODD is set in the data register DR at the beginning of the next time cycle t.sub.2.
Thus, the system of FIG. 2 requires a high operating speed for reading out each micro instruction from each of the parts EVEN and ODD of the control memory CM within each time cycle of the basic clock, and necessitates the use of a control memory CM of excellent performance. To this end, it is necessary to employ an expensive memory.